Job Description

Duration: 12 months contract

RESPONSIBILITIES:

• Work closely with design and architecture teams to scope the verification tasks and make it happen
• Responsible for all aspects of verification including RTL verification, formal verification, Coverage.
• Develop and execute on verification test plans at various levels of design hierarchy including unit and full-chip environments
• Develop high level language testbench components including stimulus drivers, BFMs, behavioral models, monitors and checkers
• Develop, simulate and debug directed and random stimulus and assembly level tests to find bugs in the low power IP design; verify the functionality and verify conformance to the spec
• Develop and analyze assertions and coverage terms. Participate in technical reviews of the specifications, design, and test plans. Identify and address areas of concern to meet design quality objectives.
• Develop tools, infrastructure, processes and flows to enable functional verification
• Maintain and improve existing functional verification infrastructure and methodology.
• When presented with Silicon issues, replicate in the pre-silicon environment, and provide debug expertise to root cause the issue and ensure complete validation
• Contribute towards and drive as needed pre-silicon and/or post-silicon verification of IP architectural and microarchitectural features
• Drive project deliverables and dependencies with IP Architects, RTL designers, and Physical Design engineers.
• Ensure the design is bug free

PREFERRED EXPERIENCE:

• Hands-on experience in UVM, System Verilog logic, Verilog design and verification
• Hands-on experience in Formal Verification and related tools
• Hands-on experience with low power design and power analysis flows
• Familiar with languages like Perl, python, C/C++ etc
• Analog-Digital co-simulation experience is plus.
• Experience in modeling hardware designs in emulators or FPGAs
• Background in power conversion and delivery for digital logic device, ideally x86 CPUs or GPUs, is a plus
• Familiarity with digital logic power management techniques (clock gating, power gating, V-F curves, on-die voltage regulation, clock integrity, etc.)
• Hardware debug methods and tools
• Experience and/or familiarity in Design-for-Debug techniques and architectures is preferred
• Work well with others in a team environment

EDUCATION:

• Bachelors Degree

About US Tech Solutions:

US Tech Solutions () is global firm providing a wide-range of talent on-demand and total workforce solutions. We are an Equal Opportunity Employer and Prohibit Discrimination and Harassment of Any Kind.

U.S. Tech Solutions, Inc. is an Affirmative Action, Equal Opportunity Employer. Our employment decisions are made without regard to race, color, religion, gender, national origin, age, disability, marital status, veteran or military status, or any other legally protected status.

Recruiter Details:

Name: Megha Arora

Email: meghaa@ustechsolutionsinc.com

Internal id: 25-36176

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