Job Description

Design Verification Engineer (CPU)

Location: Santa Clara, CA OR REMOTE

Duration: 6 Month Contract + extensions

Pay: $80/hr+ (depending on experience)

Insight Global's client is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Their team has developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

They are looking for a CPU core level feature / testplan verification engineer responsible for ISA and microarchitectural verification.

Responsibilities:

• Functional verification with emphasis on core level testplanning, stimulus development and regression debug for simulation and emulation regressions
• Understand ISA and microarchitectural specifications for the Core and create comprehensive testplans
• Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
• Develop architectural and microarchitectural coverage for core features and create stimulus for closing coverage in a timely manner
• Support design deployment across simulation and emulation platforms
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster

Required Skills and Experience:

• 5-8+ years of experience within Design Verification Engineering
• Strong background and experience with high performance OoO CPU microarchitecture
• Experience and understanding of one or more ISAs - x86, ARM or RISCV
• Experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
• Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
• Familiar with simulation, formal and emulation environments
• Hands-on with scripting (Python, PERL)
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

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