Experience in FPGA design and verification engineer, candidate must have both design and verification experience including hardware integration.
This a backfill position to pick up existing task from another FPGA engineer which requires candidate ability to learn and pick up existing design and support quickly.
Required Experience:
Strong understanding and experience in FPGA design and verification is a must.
Candidate must be familiar with UVM and system verilog.
Candidate must have experience integrating FPGA solution on hardware and design validation including simulation validation.
Matlab / Simulink FPGA design (HDLCoder / SystemGenerator) or High Level Synthesis (HLS) design experience is a plus.
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