Mixed-Signal Design Verification Engineer Job at Datum Technologies Group, San Jose, CA

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  • Datum Technologies Group
  • San Jose, CA

Job Description

Currently, we have an opening for Mixed-Signal Design Verification Engineer with our Client at San Jose, CA | On-Site . I appreciate your time and look forward to hearing from you.

Job Description: Mixed-Signal Design Verification Engineer

Location: San Jose, CA-100% Onsite

Qualifications

  • Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc.
  • Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,)
  • Familiarity with behavioral Verilog code for an analog circuit
  • Ability to write thorough test benches for digital and AMS simulators
  • Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
  • Familiarity with timing closure and static timing analysis tools
  • Experience with scan chain vector generation and verification

Responsibilities

  • Extract modeling specifications from designers
  • Development of Analog/Mixed-Signal model in System-Verilog
  • Development of UVM Testbench and developing test cases
  • Run simulation and fix the behavioral model working with Circuit designer.
  • Develop timing model for the circuit working with layout engineer.
  • This role will provide the ability to directly influence design related changes as required to meet functional specifications
  • Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design
  • Support integration of composite models into larger composite models maintained by other groups

Extract modeling specifications from designers

  • Development of Analog/Mixed-Signal model in System-Verilog
  • Development of UVM Testbench and developing test cases
  • Run simulation and fix the behavioral model working with Circuit designer.
  • Develop timing model for the circuit working with layout engineer.

Dheeraj Srivastava

Phone: 470-632-9705

Email : dheeraj@datumtg.com

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